1. Technical Field
This invention relates to the field of receiver circuits having switch-points for discriminating between the logic states of received signals, and in particular to receiver circuits having adjustable switch-point voltages.
2. Related Art
The central processing units (CPUs) of computers operate at ever increasing frequencies. To take advantage of this increased speed, buses and interface circuits must couple data to and from CPUs at higher speeds. However, transmitting data over bus connections at high frequencies generates relatively noisy signals, and the receiver circuits that couple devices to buses must be able to extract data from noisy signals quickly and accurately. In the digital realm, a receiver's accuracy reflects its ability to discriminate between signals in different logic states, which are represented by different voltage levels on the bus traces. The vast majority of these digital systems employ two voltage states to represent true and false logic states. A voltage level above a threshold or switch-point is assigned to one logic state, and a voltage level below the switch-point is assigned to the second logic state.
One source of inaccuracy in receiver circuits is the tendency of the switch-point voltage to vary with time, temperature, or processing conditions. Generally, where switching voltages must be maintained within tight tolerances, differential receivers are employed because their switch-points can be controlled more accurately than those of, for example, CMOS receivers. However, differential receivers are slower and consume more power than CMOS based circuits. In addition, they require an extra pin to couple an external reference voltage to the receiver.
Despite the speed and power advantages of CMOS technology, it has not been applied to high speed receivers with much success. This is due in large part to the difficulty in controlling switch point voltages to high tolerances in CMOS based receivers. For example, the switch point voltages on known CMOS receivers typically have tolerances of .+-.300 millivolts (mV). On the other hand, high speed, low power systems suitable for state of the art computer systems require tolerances on the order of a few tens of mVs. One known CMOS circuit incorporates circuitry to offset process variations in N-channel devices and partially mask P-channel process variations. However, this compensation scheme is static and does not compensate for variations in the switch point with time or temperature. Consequently, it does not provide compensation at the required tolerances.